| Date | Fri, 26 May 2023 16:17:39 +0300 | From | Vladimir Oltean <> | Subject | Re: [PATCH net-next 16/30] net: dsa: mt7530: move lowering port 5 RGMII driving to mt7530_setup() |
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On Mon, May 22, 2023 at 03:15:18PM +0300, arinc9.unal@gmail.com wrote: > From: Arınç ÜNAL <arinc.unal@arinc9.com> > > Move lowering Tx driving of rgmii on port 5 to right before lowering of Tx > driving of trgmii on port 6 on mt7530_setup(). > > This way, the switch should consume less power regardless of port 5 being > used. > > Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com> > Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> > ---
This patch assumes that the MAC has its TXC ticking even when PMCR_TX_EN is unset. Why would it do that?
> drivers/net/dsa/mt7530.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c > index f2c1aa9cf7f7..514e82299537 100644 > --- a/drivers/net/dsa/mt7530.c > +++ b/drivers/net/dsa/mt7530.c > @@ -933,10 +933,6 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) > /* P5 RGMII TX Clock Control: delay x */ > mt7530_write(priv, MT7530_P5RGMIITXCR, > CSR_RGMII_TXC_CFG(0x10 + tx_delay)); > - > - /* reduce P5 RGMII Tx driving, 8mA */ > - mt7530_write(priv, MT7530_IO_DRV_CR, > - P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); > } > > mt7530_write(priv, MT7530_MHWTRAP, val); > @@ -2209,6 +2205,10 @@ mt7530_setup(struct dsa_switch *ds) > > mt7530_pll_setup(priv); > > + /* Lower P5 RGMII Tx driving, 8mA */ > + mt7530_write(priv, MT7530_IO_DRV_CR, > + P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));
If you move code then preserve its alignment to the open parenthesis.
> + > /* Lower Tx driving for TRGMII path */ > for (i = 0; i < NUM_TRGMII_CTRL; i++) > mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), > -- > 2.39.2 >
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