| Date | Thu, 4 Jun 2015 11:52:59 -0700 | From | Stephen Boyd <> | Subject | Re: [PATCH v5 14/21] clk: tegra: pll: Adjust vco_min if SDM present |
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On 05/12, Rhyland Klein wrote: > From: Bill Huang <bilhuang@nvidia.com> > > This code makes use of the SDM fractional divider if present to > contrain the allowable programming range of the PLL divider register
s/contrain/constrain/
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