| Date | Wed, 13 May 2015 13:36:11 -0700 | Subject | Re: [PATCH v5 19/21] clk: tegra: Add Super Gen5 Logic | From | Benson Leung <> |
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On Tue, May 12, 2015 at 10:24 AM, Rhyland Klein <rklein@nvidia.com> wrote: > From: Bill Huang <bilhuang@nvidia.com> > > Super clock divider control and clock source mux of Tegra210 has changed > a little against prior SoCs, this patch adds Gen5 logic to address those > differences. > > Signed-off-by: Bill Huang <bilhuang@nvidia.com>
It looks like Mikko's and Thierry's EMC changes landed since you rebased :
0c1135f clk: tegra: EMC clock driver depends on EMC driver dc9fdb6 clk: tegra: Add EMC clock driver
So v5 doesn't apply cleanly anymore. Could you rebase?
> --- > v2: > - Fixed sclk divider address (0x370 -> 0x2c)
-- Benson Leung Software Engineer, Chrom* OS bleung@chromium.org
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