Messages in this thread | | | Date | Mon, 29 Apr 2024 15:12:40 +0200 | From | Borislav Petkov <> | Subject | Re: [PATCH v2 08/16] x86/mce/amd: Clean up enable_deferred_error_interrupt() |
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On Thu, Apr 04, 2024 at 10:13:51AM -0500, Yazen Ghannam wrote: > -/* Deferred error settings */ > +/* MCA Interrupt Configuration register, one per CPU */
SMCA?
> #define MSR_CU_DEF_ERR 0xC0000410 > -#define MASK_DEF_LVTOFF 0x000000F0 > -#define MASK_DEF_INT_TYPE 0x00000006 > -#define DEF_INT_TYPE_APIC 0x2 > +#define MSR_MCA_INTR_CFG 0xC0000410
You do see those other MSRs' prefixes, right?
MSR_AMD64_SMCA_...
Is this one not part of the SMCA arch?
> +#define INTR_CFG_DFR_LVT_OFFSET GENMASK_ULL(7, 4) > +#define INTR_CFG_LEGACY_DFR_INTR_TYPE GENMASK_ULL(2, 1) > #define INTR_TYPE_APIC 0x1
Ditto for its bit(s) names.
> +static u64 get_mca_intr_cfg(void) > +{ > + u64 mca_intr_cfg; > + > + if (!mce_flags.succor) > + return 0; > + > + if (rdmsrl_safe(MSR_MCA_INTR_CFG, &mca_intr_cfg)) > + return 0; > + > + return mca_intr_cfg; > +}
This is an overkill. If we add a function for every MSR we're reading...
Do this differently: prepare the value you're writing back into the INTR_CFG MSR once, save it into mca_intr_cfg and then write it on each core at the end of enable_deferred_error_interrupt().
And make u64 mca_intr_cfg static global to amd.c so that you can refer to it from outside of the functions and then you don't have to pass it around as a function param.
Thx.
-- Regards/Gruss, Boris.
https://people.kernel.org/tglx/notes-about-netiquette
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