Messages in this thread | | | Date | Wed, 24 Apr 2024 04:29:01 +0200 | From | Borislav Petkov <> | Subject | Re: [PATCH v2 05/16] x86/mce/amd: Clean up SMCA configuration |
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On Tue, Apr 23, 2024 at 03:32:00PM -0400, Yazen Ghannam wrote: > This is not the same. > > "CFG_DFR_INT_TYPE" is a register field. > > "INTR_TYPE_APIC" is a value. And this same value can be used in other register > fields.
I don't care - this was just an example of how it should look like. Like the rest of the code around the kernel and not like an obfuscated C contest mess.
> I think it's fair to just use logical AND for single bit checks instead of the > FIELD_GET() macro. > > But the FIELD_PREP() macro does help for setting bitfields. I think it's > clearer than manually doing the proper shifts and masks.
To you maybe.
Pls stick to how common code does masks generation and manipulation so that this remains readable. This FIELD* crap is not helping.
> Okay. I was thinking to keep the names shorter since they are only used in > this file. But I'll change them.
If you want to keep them shorter, then think of an overall shorter scheme of how the register *and* the fields which belong to it, should be named. But there's a point in having the same prefix for register and bits which belong to it.
> Okay. I'll include the follow up patches in the next revision of this set.
Pls do.
Thanks.
-- Regards/Gruss, Boris.
https://people.kernel.org/tglx/notes-about-netiquette
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