Messages in this thread | | | Date | Mon, 28 Oct 2013 11:34:28 +0100 | From | Andreas Werner <> | Subject | Re: [PATCH] X86: MM: Add PAT Type write-through in combination with mtrr |
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On Mon, Oct 28, 2013 at 11:17:49AM +0100, Ingo Molnar wrote: > > * Andreas Werner <wernerandy@gmx.de> wrote: > > > > IOW, you probably could use a WC buffer here too, as it would > > > combine the writes coming from the FPGA. > > > > > > Btw, there's also mtrr_add(..., MTRR_TYPE_WRTHROUGH, ) if you > > > must use a WT thing. Have you tried that? > > > > For reading i need to map the mmio with attributes that allow > > cache-line read. Therefore i use WT. For the Virtual address i use > > ioremap_cache in combination with this patch to get an effective > > memory type of "Write-Through". This allows me to read from the > > mmio with "PCIe burst". The write behaviour to this region do not > > matter. > > And regular write-back cacheable isn't sufficient because the CPU > could do things like prefetch your range automatically? > > If the reads are for packet data and not for commands, WB could > still be beneficial as it should allow even higher bandwidth. (For > non-data with real semantics WB is probably not good.) > > Thanks, > > Ingo
Yes the reads are only for packet data, the commands or configuration registers are mapped non cachable.
I´ve tried WB, but on PCIe Tracer i could not see any burst access. Thats the reason why i have created this patch.
Is there a chance to get this patch into the kernel? Or is this solution so special?
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