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SubjectRe: [PATCH] X86: MM: Add PAT Type write-through in combination with mtrr
On Sun, Oct 27, 2013 at 08:01:48PM +0100, Borislav Petkov wrote:
> On Sun, Oct 27, 2013 at 06:56:08PM +0100, Andreas Werner wrote:
> > Transmit Buffers WC (only write to that buffer)
> > i have PICe bursts on my tracer.
>
> For that you can do ioremap_wc().

Yes i am currently using ioremap_wc() and it is working
as expected.
>
> > Receive Buffers WT (only read to that buffer). I use
> > clflush_cache_range before reading from that adresses and i have PCIe
> > bursts on my tracer.
>
> That one I don't understand - why would you need a WT buffer? It only
> caches reads but you will read from it only once after it has been
> received. Why pollute the cache?
>
> IOW, you probably could use a WC buffer here too, as it would combine
> the writes coming from the FPGA.
>
> Btw, there's also mtrr_add(..., MTRR_TYPE_WRTHROUGH, ) if you must use a
> WT thing. Have you tried that?
>
For reading i need to map the mmio with attributes that allow cache-line read.
Therefore i use WT. For the Virtual address i use ioremap_cache in combination
with this patch to get an effective memory type of "Write-Through". This allows
me to read from the mmio with "PCIe burst". The write behaviour to this
region do not matter.

The clflush is used to remove stale cache lines from the cache so that
the read operation to a line goes to the MMIO device.
WT was the only one where i had bursts in reading.
A WC buffer had the same behaviour like UC on the PCIe Tracer (for reading).

I use mtrr_add to make an entry in the MTRR with a typ of WRTHROUGH
for the "receive" memory region.


> > With UC memory there are no PCIe bursts and my bandwidth is very slow.
>
> Right.
>
> --
> Regards/Gruss,
> Boris.
>
> Sent from a fat crate under my desk. Formatting is fine.
> --

Regards
Andy


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