lkml.org 
[lkml]   [2013]   [Oct]   [28]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRe: [PATCH] X86: MM: Add PAT Type write-through in combination with mtrr
On Mon, Oct 28, 2013 at 11:31:32AM +0100, Ingo Molnar wrote:
>
> * Borislav Petkov <bp@alien8.de> wrote:
>
> > On Mon, Oct 28, 2013 at 11:17:49AM +0100, Ingo Molnar wrote:
> >
> > > And regular write-back cacheable isn't sufficient because the
> > > CPU could do things like prefetch your range automatically?
> >
> > Yeah, he's doing a CLFLUSH anyway which basically makes it a
> > write-through...
>
> The CLFLUSH is done afterwards (making it a use-once thing), so WB
> might still be faster and would avoid the PAT headache ...
>
> Thanks,
>
> Ingo
What i do right now is:
1. clflush the data range to read from my mmio device
2. read the data.
On PCIe Tracer i see the pcie bursts.

If i mark the region WB and call clflush my system will crash without
any message, it just stop working.

regards
Andy


\
 
 \ /
  Last update: 2013-10-28 12:01    [W:0.101 / U:0.296 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site