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SubjectRe: [PATCH] X86: MM: Add PAT Type write-through in combination with mtrr
On Mon, Oct 28, 2013 at 11:57:31AM +0100, Borislav Petkov wrote:
> On Mon, Oct 28, 2013 at 11:34:28AM +0100, Andreas Werner wrote:
> > Yes the reads are only for packet data, the commands or configuration
> > registers are mapped non cachable.
> >
> > I´ve tried WB, but on PCIe Tracer i could not see any burst access.
> > Thats the reason why i have created this patch.
> >
> > Is there a chance to get this patch into the kernel? Or
> > is this solution so special?
>
> Ok, but your patch returns WB pat type for WT MTRR type, AFAICT.
>
> You want to do:
>
> PAT=Write-Back + MTRR=Write-Through = Effective Memory of Write-Through
>
Yes thats right.

> but you end up doing
>
> PAT=Write-Back + MTRR=Write-Through = Effective Memory of Write-Back
>
No the effective memory type is WT, check out the Intel document with the
table of Effective memory type combinations.

> What am I missing or misunderstanding?
>
> AFAICT, you want to return _PAGE_PWT for MTRR_TYPE_WRTHROUGH, no?

Yes but, there is no way in the kernel to mark a memory WT,
there is just ioremap_wc for Write combining and ioremap_cache
for Write Back, and as you can see in the Intel Effective Memory type
table, if you combine PAT=WB and MTRR=WT you will get a effective memory
of WT.

regards
Andy
>
> --
> Regards/Gruss,
> Boris.
>
> Sent from a fat crate under my desk. Formatting is fine.
> --
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