Messages in this thread | | | Date | Thu, 10 Jul 2008 11:16:34 -0700 | From | Suresh Siddha <> | Subject | [patch 00/26] x64, x2apic/intr-remap: Interrupt-remapping and x2apic support |
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x2APIC architecture provides a new x2apic mode, which allows for the increased range of processor addressability ( > 8 bit apic ID support), MSR access to APIC registers, etc. x2apic specification can be found at http://download.intel.com/design/processor/specupdt/318148.pdf (located under http://developer.intel.com/products/processor/manuals/index.htm )
Interrupt-remapping is part of Intel Virtualization Technology for Directed I/O architecture and the specification can be found from http://download.intel.com/technology/computing/vptech/Intel(r)_VT_for_Direct_IO.pdf (above link seems to be broken for the moment, but in general it should be found under http://www.intel.com/technology/virtualization/ )
Interrupt-remapping architecture enables extended Interrupt Mode on x86 platforms supporting 32-bit APIC-IDs. This infrastructure allows the existing interrupt sources such as I/OxAPICs and MSI/MSI-X devices work seamlessly with apic-id's > 8 bits. As such, this is a pre-requisite for enabling x2apic mode in the CPU.
This patchset adds 64-bit support for interrupt-remapping and x2apic, which introduces apic_ops for basic APIC ops(uncached memory Vs MSR accesses etc), new irq_chip's for supporting interrupt-remapping and new genapic for supporting IPI's, logical cluster/physical x2apic modes.
irq migration in the presence of interrupt-remapping is done from the process-context as opposed to interrupt-context. Interrupt-remapping infrastrucutre allows us to do this migration in a simple fashion (atleast for edge triggered interrupts).
Interrupt-remapping (CONFIG_INTR_REMAP) and DMA-remapping (CONFIG_DMAR) can be enabled separately.
More details in the individual patches that follow.
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> --
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