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SubjectRe: [patch 00/26] x64, x2apic/intr-remap: Interrupt-remapping and x2apic support

At a quick skim nothing looks really bad, nothing looks really bad,
but you are dealing in an area of code that could be made much nicer
and if we are going to support a noticeably different style of irq
management we need to get in some of those pending cleanups so the
code does not fall down under it's own wait.

Suresh Siddha <suresh.b.siddha@intel.com> writes:

> irq migration in the presence of interrupt-remapping is done from the
> process-context as opposed to interrupt-context. Interrupt-remapping
> infrastrucutre allows us to do this migration in a simple fashion (atleast for
> edge triggered interrupts).

Unless I have misread things this irq migration remains racy, as I did not
see any instructions that would guarantee that in flight irqs were flushed
to the cpus local apics before we cleaned up the destination.

You are sizing an array as NR_IRQS this is something there should be sufficient
existing infrastructure to avoid. Arrays sized by NR_IRQS is a significant
problem both for scaling the system up and down so ultimately we need to kill
this. For now we should not introduce any new arrays.

A lot of your code is generic, and some of it is for just x86_64. Since the
cpus are capable of running in 32bit mode. We really need to implement x86_32
and x86_64 support in the same code base. Which I believe means factoring out
pieces of io_apic_N.c into things such as msi.c that can be shared between the
two architectures.

Eric



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