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    SubjectRe: [PATCH 2/7] arm64: dts: qcom: sm8250: Add cpufreq hw node
    On Tue, Sep 8, 2020 at 1:27 PM Manivannan Sadhasivam
    <manivannan.sadhasivam@linaro.org> wrote:
    >
    > From: Bjorn Andersson <bjorn.andersson@linaro.org>
    >
    > Add cpufreq HW device node to scale 4-Silver/3-Gold/1-Gold+ cores
    > on SM8250 SoCs.
    >
    > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
    > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>


    Reviewed-by: Amit Kucheria <amitk@kernel.org>


    > ---
    > arch/arm64/boot/dts/qcom/sm8250.dtsi | 22 ++++++++++++++++++++++
    > 1 file changed, 22 insertions(+)
    >
    > diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
    > index e7d139e1a6ce..aafb46a26a9c 100644
    > --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
    > +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
    > @@ -87,6 +87,7 @@
    > reg = <0x0 0x0>;
    > enable-method = "psci";
    > next-level-cache = <&L2_0>;
    > + qcom,freq-domain = <&cpufreq_hw 0>;
    > L2_0: l2-cache {
    > compatible = "cache";
    > next-level-cache = <&L3_0>;
    > @@ -102,6 +103,7 @@
    > reg = <0x0 0x100>;
    > enable-method = "psci";
    > next-level-cache = <&L2_100>;
    > + qcom,freq-domain = <&cpufreq_hw 0>;
    > L2_100: l2-cache {
    > compatible = "cache";
    > next-level-cache = <&L3_0>;
    > @@ -114,6 +116,7 @@
    > reg = <0x0 0x200>;
    > enable-method = "psci";
    > next-level-cache = <&L2_200>;
    > + qcom,freq-domain = <&cpufreq_hw 0>;
    > L2_200: l2-cache {
    > compatible = "cache";
    > next-level-cache = <&L3_0>;
    > @@ -126,6 +129,7 @@
    > reg = <0x0 0x300>;
    > enable-method = "psci";
    > next-level-cache = <&L2_300>;
    > + qcom,freq-domain = <&cpufreq_hw 0>;
    > L2_300: l2-cache {
    > compatible = "cache";
    > next-level-cache = <&L3_0>;
    > @@ -138,6 +142,7 @@
    > reg = <0x0 0x400>;
    > enable-method = "psci";
    > next-level-cache = <&L2_400>;
    > + qcom,freq-domain = <&cpufreq_hw 1>;
    > L2_400: l2-cache {
    > compatible = "cache";
    > next-level-cache = <&L3_0>;
    > @@ -150,6 +155,7 @@
    > reg = <0x0 0x500>;
    > enable-method = "psci";
    > next-level-cache = <&L2_500>;
    > + qcom,freq-domain = <&cpufreq_hw 1>;
    > L2_500: l2-cache {
    > compatible = "cache";
    > next-level-cache = <&L3_0>;
    > @@ -163,6 +169,7 @@
    > reg = <0x0 0x600>;
    > enable-method = "psci";
    > next-level-cache = <&L2_600>;
    > + qcom,freq-domain = <&cpufreq_hw 1>;
    > L2_600: l2-cache {
    > compatible = "cache";
    > next-level-cache = <&L3_0>;
    > @@ -175,6 +182,7 @@
    > reg = <0x0 0x700>;
    > enable-method = "psci";
    > next-level-cache = <&L2_700>;
    > + qcom,freq-domain = <&cpufreq_hw 2>;
    > L2_700: l2-cache {
    > compatible = "cache";
    > next-level-cache = <&L3_0>;
    > @@ -2076,6 +2084,20 @@
    > };
    > };
    > };
    > +
    > + cpufreq_hw: cpufreq@18591000 {
    > + compatible = "qcom,sm8250-epss";
    > + reg = <0 0x18591000 0 0x1000>,
    > + <0 0x18592000 0 0x1000>,
    > + <0 0x18593000 0 0x1000>;
    > + reg-names = "freq-domain0", "freq-domain1",
    > + "freq-domain2";
    > +
    > + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
    > + clock-names = "xo", "alternate";
    > +
    > + #freq-domain-cells = <1>;
    > + };
    > };
    >
    > timer {
    > --
    > 2.17.1
    >

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