Messages in this thread Patch in this message | | | From | Li Ming <> | Subject | [RFC PATCH 3/6] PCI/AER: Enable RCEC to report internal error for CXL root port | Date | Wed, 13 Mar 2024 08:35:59 +0000 |
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Per CXl r3.1 section 12.2.2, CXL.cachemem protocol erros detected by CXL root port could be logged in RCEC AER Extended Capability as PCI_ERR_UNC_INTN or PCI_ERR_COR_INTERNAL. Unmask these errors for that case.
Signed-off-by: Li Ming <ming4.li@intel.com> --- drivers/pci/pcie/aer.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 42a3bd35a3e1..364c74e47273 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -985,7 +985,7 @@ static bool cxl_error_is_native(struct pci_dev *dev) { struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); - return (pcie_ports_native || host->native_aer); + return (pcie_ports_native || host->native_aer) && host->is_cxl; } static bool is_internal_error(struct aer_err_info *info) @@ -1041,8 +1041,13 @@ static int handles_cxl_error_iter(struct pci_dev *dev, void *data) { bool *handles_cxl = data; - if (!*handles_cxl) - *handles_cxl = is_cxl_mem_dev(dev) && cxl_error_is_native(dev); + if (!*handles_cxl && cxl_error_is_native(dev)) { + if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END && + dev->rcec && is_cxl_mem_dev(dev)) + *handles_cxl = true; + if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) + *handles_cxl = true; + } /* Non-zero terminates iteration */ return *handles_cxl; @@ -1054,13 +1059,18 @@ static bool handles_cxl_errors(struct pci_dev *rcec) if (pci_pcie_type(rcec) == PCI_EXP_TYPE_RC_EC && pcie_aer_is_native(rcec)) - pcie_walk_rcec(rcec, handles_cxl_error_iter, &handles_cxl); + pcie_walk_rcec_all(rcec, handles_cxl_error_iter, &handles_cxl); return handles_cxl; } -static void cxl_rch_enable_rcec(struct pci_dev *rcec) +static void cxl_enable_rcec(struct pci_dev *rcec) { + /* + * Enable RCEC's internal error report for two cases: + * 1. RCiEP detected CXL.cachemem protocol errors + * 2. CXL root port detected CXL.cachemem protocol errors. + */ if (!handles_cxl_errors(rcec)) return; @@ -1069,7 +1079,7 @@ static void cxl_rch_enable_rcec(struct pci_dev *rcec) } #else -static inline void cxl_rch_enable_rcec(struct pci_dev *dev) { } +static inline void cxl_enable_rcec(struct pci_dev *dev) { } static inline void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info) { } #endif @@ -1494,7 +1504,7 @@ static int aer_probe(struct pcie_device *dev) return status; } - cxl_rch_enable_rcec(port); + cxl_enable_rcec(port); aer_enable_rootport(rpc); pci_info(port, "enabled with IRQ %d\n", dev->irq); return 0; -- 2.40.1
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