Messages in this thread Patch in this message | | | From | Li Ming <> | Subject | [RFC PATCH 2/6] PCI/CXL: A new attribute to indicate CXL-capable host bridge | Date | Wed, 13 Mar 2024 08:35:58 +0000 |
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Introduce a new attribute called 'is_cxl' in struct pci_host_bridge to indicate if the PCI host bridge is CXl capable.
Suggested-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Li Ming <ming4.li@intel.com> --- drivers/acpi/pci_root.c | 1 + include/linux/pci.h | 1 + 2 files changed, 2 insertions(+)
diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c index 58b89b8d950e..4ab0dc8450ce 100644 --- a/drivers/acpi/pci_root.c +++ b/drivers/acpi/pci_root.c @@ -1034,6 +1034,7 @@ struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root, goto out_release_info; host_bridge = to_pci_host_bridge(bus->bridge); + host_bridge->is_cxl = is_cxl(root); if (!(root->osc_control_set & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL)) host_bridge->native_pcie_hotplug = 0; if (!(root->osc_control_set & OSC_PCI_SHPC_NATIVE_HP_CONTROL)) diff --git a/include/linux/pci.h b/include/linux/pci.h index bf6c02bee49f..bbe90e730285 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -587,6 +587,7 @@ struct pci_host_bridge { unsigned int preserve_config:1; /* Preserve FW resource setup */ unsigned int size_windows:1; /* Enable root bus sizing */ unsigned int msi_domain:1; /* Bridge wants MSI domain */ + unsigned int is_cxl:1; /* CXL capable Host Bridge */ /* Resource alignment requirements */ resource_size_t (*align_resource)(struct pci_dev *dev, -- 2.40.1
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