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SubjectRe: [RFC PATCH 4/6] PCI/AER: Extend RCH RAS error handling to support VH topology case
Li Ming wrote:
> When RCEC captures CXL.cachemem protocol errors detected by CXL root
> port, the recommendation from CXL r3.1 9.18.1.5 is :
>
> "Probe all CXL Downstream Ports and determine whether they have logged an
> error in the CXL.io or CXL.cachemem status registers."
>
> The flow is similar with RCH RAS error handling, so reuse it to support
> above case.
>
> Signed-off-by: Li Ming <ming4.li@intel.com>
> ---
> drivers/pci/pcie/aer.c | 20 ++++++++++++--------
> 1 file changed, 12 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
> index 364c74e47273..79bfa5fb78f4 100644
> --- a/drivers/pci/pcie/aer.c
> +++ b/drivers/pci/pcie/aer.c
> @@ -996,11 +996,15 @@ static bool is_internal_error(struct aer_err_info *info)
> return info->status & PCI_ERR_UNC_INTN;
> }
>
> -static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data)
> +static int cxl_handle_error_iter(struct pci_dev *dev, void *data)
> {
> struct aer_err_info *info = (struct aer_err_info *)data;
> const struct pci_error_handlers *err_handler;
>
> + /* Skip the RCiEP devices not associating with RCEC */
> + if ((pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) &&
> + !dev->rcec)
> + return 0;
> if (!is_cxl_mem_dev(dev) || !cxl_error_is_native(dev))
> return 0;

is_cxl_mem_dev(dev) will always be false in the VH case, so how does
this change help the VH case?

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