Messages in this thread Patch in this message | | | From | Bhaskar Chowdhury <> | Subject | [PATCH] coresight-pmu.h: Fix a typo | Date | Fri, 26 Mar 2021 19:52:44 +0530 |
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s/orignally/originally/
Signed-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com> --- include/linux/coresight-pmu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h index 4ac5c081af93..2d5c29e3cb8a 100644 --- a/include/linux/coresight-pmu.h +++ b/include/linux/coresight-pmu.h @@ -14,7 +14,7 @@ * Below are the definition of bit offsets for perf option, and works as * arbitrary values for all ETM versions. * - * Most of them are orignally from ETMv3.5/PTM's ETMCR config, therefore, + * Most of them are originally from ETMv3.5/PTM's ETMCR config, therefore, * ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and * directly use below macros as config bits. */ -- 2.26.2
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