Messages in this thread | | | From | Mathieu Poirier <> | Date | Mon, 29 Mar 2021 08:38:15 -0600 | Subject | Re: [PATCH] coresight-pmu.h: Fix a typo |
| |
On Fri, 26 Mar 2021 at 13:53, Bhaskar Chowdhury <unixbhaskar@gmail.com> wrote: > > On 09:32 Fri 26 Mar 2021, Mathieu Poirier wrote: > >Hi Bhaskar, > > > >On Fri, Mar 26, 2021 at 07:52:44PM +0530, Bhaskar Chowdhury wrote: > >> > >> s/orignally/originally/ > > > >Even if the change is trivial this changelog is insufficient. Moreover, if you > >found the problem with an automated tool, please add the name of the tool to the > >changelog. > > > Oh Hi! > > I think the changelog is sufficient enough to conveying the triviality of this > change.What's the point of writing unnecessary history , when a simple > statement can do the work. >
All I'm asking for is a one line description, nothing more. Otherwise this patch will not get applied.
> These are hand picked ...there is no point mentioning the tool in the > changelog..it is all age old UNIX/Linux tool , nothing special. > > >Thanks, > >Mathieu > > > >> > >> Signed-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com> > >> --- > >> include/linux/coresight-pmu.h | 2 +- > >> 1 file changed, 1 insertion(+), 1 deletion(-) > >> > >> diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h > >> index 4ac5c081af93..2d5c29e3cb8a 100644 > >> --- a/include/linux/coresight-pmu.h > >> +++ b/include/linux/coresight-pmu.h > >> @@ -14,7 +14,7 @@ > >> * Below are the definition of bit offsets for perf option, and works as > >> * arbitrary values for all ETM versions. > >> * > >> - * Most of them are orignally from ETMv3.5/PTM's ETMCR config, therefore, > >> + * Most of them are originally from ETMv3.5/PTM's ETMCR config, therefore, > >> * ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and > >> * directly use below macros as config bits. > >> */ > >> -- > >> 2.26.2 > >>
| |