Messages in this thread | | | From | kan.liang@linux ... | Subject | [PATCH 00/12] perf core PMU support for Sapphire Rapids | Date | Tue, 19 Jan 2021 12:38:19 -0800 |
| |
From: Kan Liang <kan.liang@linux.intel.com>
Intel Sapphire Rapids server is the successor of the Intel Ice Lake server. The enabling code is based on Ice Lake, but there are several new features introduced. - The event encoding is changed and simplified. - A new Precise Distribution (PDist) facility. - Two new data source fields, data block & address block, are added in the PEBS Memory Info Record for the load latency event. - A new store Latency facility is introduced. - The layout of access latency field of PEBS Memory Info Record has been changed. Two latency, instruction latency and cache access latency are recorded. To support the new latency fields, a new sample type, PERF_SAMPLE_WEIGHT_EXT, is introduced. - Extends the PERF_METRICS MSR to feature TMA method level 2 metrics.
Besides the Sapphire Rapids specific features, the CPUID 10.ECX extension is also supported, which is available for all platforms with Architectural Performance Monitoring Version 5.
The full description for the SPR features can be found at Intel Architecture Instruction Set Extensions and Future Features Programming Reference, 319433-041 (and later).
Both kernel and perf tool patches are included in the V1.
Kan Liang (12): perf/core: Add PERF_SAMPLE_WEIGHT_EXT perf/x86/intel: Factor out intel_update_topdown_event() perf/x86/intel: Add perf core PMU support for Sapphire Rapids perf/x86/intel: Support CPUID 10.ECX to disable fixed counters tools headers uapi: Update tools's copy of linux/perf_event.h perf tools: Support data block and addr block perf c2c: Support data block and addr block perf tools: Support PERF_SAMPLE_WEIGHT_EXT perf report: Support instruction latency perf test: Support PERF_SAMPLE_WEIGHT_EXT perf stat: Support L2 Topdown events perf, tools: Update topdown documentation for Sapphire Rapids
arch/x86/events/core.c | 8 +- arch/x86/events/intel/core.c | 383 ++++++++++++++++++++++++++++-- arch/x86/events/intel/ds.c | 112 ++++++++- arch/x86/events/perf_event.h | 17 +- arch/x86/include/asm/perf_event.h | 16 +- include/linux/perf_event.h | 1 + include/uapi/linux/perf_event.h | 30 ++- kernel/events/core.c | 6 + tools/include/uapi/linux/perf_event.h | 30 ++- tools/perf/Documentation/perf-report.txt | 9 +- tools/perf/Documentation/perf-stat.txt | 14 +- tools/perf/Documentation/topdown.txt | 78 +++++- tools/perf/arch/x86/util/Build | 1 + tools/perf/arch/x86/util/mem-events.c | 44 ++++ tools/perf/builtin-c2c.c | 3 + tools/perf/builtin-mem.c | 2 +- tools/perf/builtin-stat.c | 34 ++- tools/perf/tests/sample-parsing.c | 3 +- tools/perf/util/event.h | 1 + tools/perf/util/evsel.c | 24 +- tools/perf/util/evsel.h | 1 + tools/perf/util/hist.c | 13 +- tools/perf/util/hist.h | 3 + tools/perf/util/mem-events.c | 36 +++ tools/perf/util/mem-events.h | 5 + tools/perf/util/perf_event_attr_fprintf.c | 2 +- tools/perf/util/record.c | 4 +- tools/perf/util/session.c | 3 + tools/perf/util/sort.c | 83 ++++++- tools/perf/util/sort.h | 4 + tools/perf/util/stat-shadow.c | 92 +++++++ tools/perf/util/stat.c | 4 + tools/perf/util/stat.h | 9 + tools/perf/util/synthetic-events.c | 8 + 34 files changed, 1024 insertions(+), 59 deletions(-) create mode 100644 tools/perf/arch/x86/util/mem-events.c
-- 2.7.4
| |