Messages in this thread Patch in this message | | | Date | Tue, 26 Jan 2021 16:44:23 +0100 | From | Peter Zijlstra <> | Subject | Re: [PATCH 04/12] perf/x86/intel: Support CPUID 10.ECX to disable fixed counters |
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On Tue, Jan 19, 2021 at 12:38:23PM -0800, kan.liang@linux.intel.com wrote: > @@ -5228,7 +5231,7 @@ __init int intel_pmu_init(void) > * Check whether the Architectural PerfMon supports > * Branch Misses Retired hw_event or not. > */ > - cpuid(10, &eax.full, &ebx.full, &unused, &edx.full); > + cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full); > if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT) > return -ENODEV; > > @@ -5255,8 +5258,16 @@ __init int intel_pmu_init(void) > if (version > 1) { > int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR); > > - x86_pmu.num_counters_fixed = > - max((int)edx.split.num_counters_fixed, assume); > + if (!fixed_mask) { > + x86_pmu.num_counters_fixed = > + max((int)edx.split.num_counters_fixed, assume); > + } else { > + /* > + * The fixed-purpose counters are enumerated in the ECX > + * since V5 perfmon. > + */
But that's not what the code implements.
> + x86_pmu.num_counters_fixed = fls(fixed_mask); > + } > }
What you were looking for is something like this:
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index fe940082d49a..9ad42cb59606 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -4817,6 +4817,13 @@ __init int intel_pmu_init(void) x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, assume); + + if (version >= 5) { + /* + * V5 and later provide a fixed counter mask. + */ + x86_pmu.num_counters_fixed = fls(fixed_mask); + } } if (boot_cpu_has(X86_FEATURE_PDCM)) {
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