lkml.org 
[lkml]   [2020]   [Jun]   [26]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
Patch in this message
/
From
Subject[PATCH V2 03/23] perf/x86/intel/lbr: Add a function pointer for LBR read
Date
From: Kan Liang <kan.liang@linux.intel.com>

The method to read Architectural LBRs is different from previous
model-specific LBR. Perf has to implement a different function.

A function pointer for LBR read is introduced. Perf should initialize
the corresponding function at boot time, and avoid checking lbr_format
at run time.

The current 64-bit LBR read function is set as default.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
arch/x86/events/intel/core.c | 6 +++++-
arch/x86/events/intel/lbr.c | 9 +++------
arch/x86/events/perf_event.h | 5 +++++
3 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index c2ab13a..e08a591 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3953,6 +3953,7 @@ static __initconst const struct x86_pmu core_pmu = {
.check_period = intel_pmu_check_period,

.lbr_reset = intel_pmu_lbr_reset_64,
+ .lbr_read = intel_pmu_lbr_read_64,
};

static __initconst const struct x86_pmu intel_pmu = {
@@ -4000,6 +4001,7 @@ static __initconst const struct x86_pmu intel_pmu = {
.aux_output_match = intel_pmu_aux_output_match,

.lbr_reset = intel_pmu_lbr_reset_64,
+ .lbr_read = intel_pmu_lbr_read_64,
};

static __init void intel_clovertown_quirk(void)
@@ -4626,8 +4628,10 @@ __init int intel_pmu_init(void)
x86_pmu.intel_cap.capabilities = capabilities;
}

- if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32)
+ if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) {
x86_pmu.lbr_reset = intel_pmu_lbr_reset_32;
+ x86_pmu.lbr_read = intel_pmu_lbr_read_32;
+ }

intel_ds_init();

diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index abca269..42466a0 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -542,7 +542,7 @@ void intel_pmu_lbr_disable_all(void)
__intel_pmu_lbr_disable();
}

-static void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc)
+void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc)
{
unsigned long mask = x86_pmu.lbr_nr - 1;
u64 tos = intel_pmu_lbr_tos();
@@ -579,7 +579,7 @@ static void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc)
* is the same as the linear address, allowing us to merge the LIP and EIP
* LBR formats.
*/
-static void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc)
+void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc)
{
bool need_info = false, call_stack = false;
unsigned long mask = x86_pmu.lbr_nr - 1;
@@ -683,10 +683,7 @@ void intel_pmu_lbr_read(void)
if (!cpuc->lbr_users || cpuc->lbr_users == cpuc->lbr_pebs_users)
return;

- if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32)
- intel_pmu_lbr_read_32(cpuc);
- else
- intel_pmu_lbr_read_64(cpuc);
+ x86_pmu.lbr_read(cpuc);

intel_pmu_lbr_filter(cpuc);
}
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 97e1457..70a0b5e 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -692,6 +692,7 @@ struct x86_pmu {
bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */

void (*lbr_reset)(void);
+ void (*lbr_read)(struct cpu_hw_events *cpuc);

/*
* Intel PT/LBR/BTS are exclusive
@@ -1081,6 +1082,10 @@ void intel_pmu_lbr_disable_all(void);

void intel_pmu_lbr_read(void);

+void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc);
+
+void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc);
+
void intel_pmu_lbr_init_core(void);

void intel_pmu_lbr_init_nhm(void);
--
2.7.4
\
 
 \ /
  Last update: 2020-06-26 20:25    [W:0.116 / U:6.464 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site