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SubjectRe: [PATCH V2 08/23] perf/x86: Expose CPUID enumeration bits for arch LBR
On Fri, Jun 26, 2020 at 11:20:05AM -0700, kan.liang@linux.intel.com wrote:
> From: Kan Liang <kan.liang@linux.intel.com>
>
> The LBR capabilities of Architecture LBR are retrieved from the CPUID
> enumeration once at boot time. The capabilities have to be saved for
> future usage.
>
> Several new fields are added into structure x86_pmu to indicate the
> capabilities. The fields will be used in the following patches.
>
> Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
> ---
> arch/x86/events/perf_event.h | 5 +++++
> arch/x86/include/asm/perf_event.h | 40 +++++++++++++++++++++++++++++++++++++++
> 2 files changed, 45 insertions(+)
>
> diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
> index d04818b..9b0e533 100644
> --- a/arch/x86/events/perf_event.h
> +++ b/arch/x86/events/perf_event.h
> @@ -690,6 +690,11 @@ struct x86_pmu {
> const int *lbr_sel_map; /* lbr_select mappings */
> bool lbr_double_abort; /* duplicated lbr aborts */
> bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */
> + bool arch_lbr; /* Arch LBR supported */
> +
> + union cpuid28_eax lbr_eax;
> + union cpuid28_ebx lbr_ebx;
> + union cpuid28_ecx lbr_ecx;

Why keep the full CPUID leaf here? What's wrong with something like:

unsigned int lbr_depth_mask:8;
unsigned int lbr_deep_c_reset:1;
unsigned int lbr_lip:1;
unsigned int lbr_cpl:1;
unsigned int lbr_filter:1;
unsigned int lbr_call_stack:1;
unsigned int lbr_mispred:1;
unsigned int lbr_timed_lbr:1;
unsigned int lbr_br_type:1;

That's only 2 bytes, instead of 24.

> void (*lbr_reset)(void);
> void (*lbr_read)(struct cpu_hw_events *cpuc);

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