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Subject[PATCH V2 11/23] perf/x86/intel/lbr: Unify the stored format of LBR information
Date
From: Kan Liang <kan.liang@linux.intel.com>

Current LBR information in the structure x86_perf_task_context is stored
in a different format from the PEBS LBR record and Architecture LBR,
which prevents the sharing of the common codes.

Use the format of the PEBS LBR record as a unified format. Use a generic
name lbr_entry to replace pebs_lbr_entry.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
arch/x86/events/intel/ds.c | 4 ++--
arch/x86/events/intel/lbr.c | 12 ++++++------
arch/x86/events/perf_event.h | 4 +---
arch/x86/include/asm/perf_event.h | 4 ++--
4 files changed, 11 insertions(+), 13 deletions(-)

diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index dc43cc1..0d33f85 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -954,7 +954,7 @@ static void adaptive_pebs_record_size_update(void)
if (pebs_data_cfg & PEBS_DATACFG_XMMS)
sz += sizeof(struct pebs_xmm);
if (pebs_data_cfg & PEBS_DATACFG_LBRS)
- sz += x86_pmu.lbr_nr * sizeof(struct pebs_lbr_entry);
+ sz += x86_pmu.lbr_nr * sizeof(struct lbr_entry);

cpuc->pebs_record_size = sz;
}
@@ -1598,7 +1598,7 @@ static void setup_pebs_adaptive_sample_data(struct perf_event *event,
struct pebs_lbr *lbr = next_record;
int num_lbr = ((format_size >> PEBS_DATACFG_LBR_SHIFT)
& 0xff) + 1;
- next_record = next_record + num_lbr*sizeof(struct pebs_lbr_entry);
+ next_record = next_record + num_lbr * sizeof(struct lbr_entry);

if (has_branch_stack(event)) {
intel_pmu_store_pebs_lbrs(lbr);
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index 918f89d..3d5fec4 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -371,11 +371,11 @@ void intel_pmu_lbr_restore(void *ctx)
mask = x86_pmu.lbr_nr - 1;
for (i = 0; i < task_ctx->valid_lbrs; i++) {
lbr_idx = (tos - i) & mask;
- wrlbr_from(lbr_idx, task_ctx->lbr_from[i]);
- wrlbr_to (lbr_idx, task_ctx->lbr_to[i]);
+ wrlbr_from(lbr_idx, task_ctx->lbr[i].from);
+ wrlbr_to(lbr_idx, task_ctx->lbr[i].to);

if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO)
- wrmsrl(MSR_LBR_INFO_0 + lbr_idx, task_ctx->lbr_info[i]);
+ wrmsrl(MSR_LBR_INFO_0 + lbr_idx, task_ctx->lbr[i].info);
}

for (; i < x86_pmu.lbr_nr; i++) {
@@ -435,10 +435,10 @@ void intel_pmu_lbr_save(void *ctx)
from = rdlbr_from(lbr_idx);
if (!from)
break;
- task_ctx->lbr_from[i] = from;
- task_ctx->lbr_to[i] = rdlbr_to(lbr_idx);
+ task_ctx->lbr[i].from = from;
+ task_ctx->lbr[i].to = rdlbr_to(lbr_idx);
if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO)
- rdmsrl(MSR_LBR_INFO_0 + lbr_idx, task_ctx->lbr_info[i]);
+ rdmsrl(MSR_LBR_INFO_0 + lbr_idx, task_ctx->lbr[i].info);
}
task_ctx->valid_lbrs = i;
task_ctx->tos = tos;
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 62fba45..fd16ed3 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -755,12 +755,10 @@ struct x86_perf_task_context_opt {
};

struct x86_perf_task_context {
- u64 lbr_from[MAX_LBR_ENTRIES];
- u64 lbr_to[MAX_LBR_ENTRIES];
- u64 lbr_info[MAX_LBR_ENTRIES];
int tos;
int valid_lbrs;
struct x86_perf_task_context_opt opt;
+ struct lbr_entry lbr[MAX_LBR_ENTRIES];
};

#define x86_add_quirk(func_) \
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index d33cc82..7266aef 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -262,12 +262,12 @@ struct pebs_xmm {
u64 xmm[16*2]; /* two entries for each register */
};

-struct pebs_lbr_entry {
+struct lbr_entry {
u64 from, to, info;
};

struct pebs_lbr {
- struct pebs_lbr_entry lbr[0]; /* Variable length */
+ struct lbr_entry lbr[0]; /* Variable length */
};

/*
--
2.7.4
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