Messages in this thread Patch in this message | | | From | Aapo Vienamo <> | Subject | [PATCH 01/10] mmc: tegra: Poll for calibration completion | Date | Tue, 24 Jul 2018 17:29:42 +0300 |
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Implement polling with 10 ms timeout for automatic pad drive strength calibration.
Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> --- drivers/mmc/host/sdhci-tegra.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index f108c48..e40ca43 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -49,6 +49,9 @@ #define SDHCI_AUTO_CAL_START BIT(31) #define SDHCI_AUTO_CAL_ENABLE BIT(29) +#define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec +#define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) + #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) @@ -198,13 +201,24 @@ static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) { - u32 val; + unsigned timeout = 10; + u32 reg; - mdelay(1); + reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); + reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; + sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); + udelay(1); + + do { + reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_STATUS); + if (!(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE)) + break; + mdelay(1); + timeout--; + } while (timeout); - val = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); - val |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; - sdhci_writel(host,val, SDHCI_TEGRA_AUTO_CAL_CONFIG); + if (timeout == 0) + dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); } static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) -- 2.7.4
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