Messages in this thread | | | From | Namhyung Kim <> | Subject | Re: [Patch v1 06/10] perf/x86: add support for PEBS Precise Store | Date | Wed, 31 Oct 2012 14:21:21 +0900 |
| |
On Mon, 29 Oct 2012 16:15:48 +0100, Stephane Eranian wrote: > This patch adds support for PEBS Precise Store > which is available on Intel Sandy Bridge and > Ivy Bridge processors. > > To use Precise store, the proper PEBS event > must be used: mem_trans_retired:precise_stores. > For the perf tool, the generic mem-stores event > exported via sysfs can be used directly.
Just trivial nitpicks..
> > Signed-off-by: Stephane Eranian <eranian@google.com> > --- [snip] > @@ -486,6 +524,7 @@ struct event_constraint intel_snb_pebs_event_constraints[] = { > INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */ > INTEL_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */ > INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */ > + INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */ > INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */ > INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ > INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ > @@ -500,6 +539,7 @@ struct event_constraint intel_ivb_pebs_event_constraints[] = { > INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */ > INTEL_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */ > INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */ > + INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
White-space damaged? Oh, it seems already broken with spaces.
> INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */ > INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ > INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ [snip] > @@ -672,7 +715,7 @@ static void __intel_pmu_pebs_event(struct perf_event *event, > /* > * if PEBS-LL or PreciseStore > */ > - if (fll) { > + if (fll || fst) { > if (sample_type & PERF_SAMPLE_ADDR) > data.addr = pebs->dla; > > @@ -688,6 +731,8 @@ static void __intel_pmu_pebs_event(struct perf_event *event, > if (sample_type & PERF_SAMPLE_DSRC) { > if (fll) > data.dsrc.val = load_latency_data(pebs->dse); > + else if (fst)
Looks like it can be converted to a plain 'else'.
Thanks, Namhyung
| |