Messages in this thread | | | Date | Mon, 29 Oct 2012 14:16:15 -0700 | From | Andi Kleen <> | Subject | Re: [Patch v1 04/10] perf/x86: add memory profiling via PEBS Load Latency |
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> > Why do you need to replace the whole table? > > > Because I am extending them with one or two events based on cpu > model. That was the easiest way of doing this instead of playing > some kind of malloc+copy trick.
I did malloc and copy.
> > > BTW I still think my approach in the v4 Haswell patchkit > > is simpler and didn't rely on hardcoding these events. > > > I don't care about those events. As I found out, they are not even > used by perf because they are all hardcoded and that's what gets > used. I assume they are exposed for reference only. I don't object > to that. But I think the right mechanism would be one where you > can add events at boot time based on CPU model. It could be used > to add the common events as well in the common part of the init > code.
Yes that's what I did.
I don't think copying everything for everything new is a good approach.
-Andi
-- ak@linux.intel.com -- Speaking for myself only
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