Messages in this thread | | | From | David Daney <> | Subject | [PATCH 0/6] MIPS: perf: Make perf work for 64-bit/Octeon counters. | Date | Thu, 6 Jan 2011 18:35:01 -0800 |
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The existing MIPS perf hardware counter support only handles 32-bit wide counters. Some CPUs (like Octeon) have the 64-bit wide variety. This patch set allows perf to work on Octeon, and I hope not break existing systems. I have not tested it on non-Octeon systems, so it would be good if someone could test that.
Summary of the patches:
1) Fix faulty Octeon interrupt controller code.
2) Add some register definitions.
3,4) Clean up existing code.
5) 64-bit perf counter support.
6) Octeon perf event bindings.
Patch 4/6 is the biggest and has the highest chance of having broken something.
This patch set depends on a couple of others that have previously been sent to Ralf:
http://patchwork.linux-mips.org/patch/1927/ http://patchwork.linux-mips.org/patch/1850/ http://patchwork.linux-mips.org/patch/1851/ http://patchwork.linux-mips.org/patch/1852/ http://patchwork.linux-mips.org/patch/1853/ http://patchwork.linux-mips.org/patch/1854/
David Daney (6): MIPS: Octeon: Enable per-CPU IRQs on all CPUs. MIPS: Add accessor macros for 64-bit performance counter registers. MIPS: perf: Cleanup formatting in arch/mips/kernel/perf_event.c MIPS: perf: Reorganize contents of perf support files. MIPS: perf: Add support for 64-bit perf counters. MIPS: perf: Add Octeon support for hardware perf.
arch/mips/Kconfig | 2 +- arch/mips/cavium-octeon/octeon-irq.c | 30 +- arch/mips/cavium-octeon/smp.c | 10 + arch/mips/include/asm/mipsregs.h | 8 + arch/mips/kernel/Makefile | 5 +- arch/mips/kernel/perf_event.c | 521 +-------------- arch/mips/kernel/perf_event_mipsxx.c | 1265 +++++++++++++++++++++++++--------- 7 files changed, 977 insertions(+), 864 deletions(-)
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Ingo Molnar <mingo@elte.hu> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> -- 1.7.2.3
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