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SubjectRe: [PATCH 5/6] MIPS: perf: Add support for 64-bit perf counters.
On 01/20/2011 02:06 AM, Deng-Cheng Zhu wrote:
> 2011/1/7 David Daney<ddaney@caviumnetworks.com>:
>> @@ -294,14 +519,29 @@ static void mipspmu_read(struct perf_event *event)
>>
>> static void mipspmu_enable(struct pmu *pmu)
>> {
>> - if (mipspmu)
>> - mipspmu->start();
>> +#ifdef CONFIG_MIPS_MT_SMP
>> + write_unlock(&pmuint_rwlock);
>> +#endif
>> + resume_local_counters();
>> }
>
> When working with CONFIG_MIPS_MT_SMP, the compiler says 'pmuint_rwlock
> undeclared' because of its improper place of definition.
>

OK, I will try to fix it.


>
>> @@ -1550,10 +1462,30 @@ init_hw_perf_events(void)
>> return -ENODEV;
>> }
>>
>> - if (mipspmu)
>> - pr_cont("%s PMU enabled, %d counters available to each "
>> - "CPU, irq %d%s\n", mipspmu->name, counters, irq,
>> - irq< 0 ? " (share with timer interrupt)" : "");
>> + mipspmu.num_counters = counters;
>> + mipspmu.irq = irq;
>> +
>> + if (read_c0_perfctrl0()& M_PERFCTL_WIDE) {
>> + mipspmu.max_period = (1ULL<< 63) - 1;
>> + mipspmu.valid_count = (1ULL<< 63) - 1;
>> + mipspmu.overflow = 1ULL<< 63;
>> + mipspmu.read_counter = mipsxx_pmu_read_counter_64;
>> + mipspmu.write_counter = mipsxx_pmu_write_counter_64;
>> + counter_bits = 64;
>> + } else {
>> + mipspmu.max_period = (1ULL<< 32) - 1;
>> + mipspmu.valid_count = (1ULL<< 31) - 1;
>> + mipspmu.overflow = 1ULL<< 31;
>> + mipspmu.read_counter = mipsxx_pmu_read_counter;
>> + mipspmu.write_counter = mipsxx_pmu_write_counter;
>> + counter_bits = 32;
>> + }
>> +
>> + on_each_cpu(reset_counters, (void *)(long)counters, 1);
>> +
>> + pr_cont("%s PMU enabled, %d %d-bit counters available to each "
>> + "CPU, irq %d%s\n", mipspmu.name, counters, counter_bits, irq,
>> + irq< 0 ? " (share with timer interrupt)" : "");
>>
>> perf_pmu_register(&pmu);
>>
>
> perf_pmu_register(&pmu) should be now changed to perf_pmu_register(&pmu,
> "cpu", PERF_TYPE_RAW).

Yes, I already have that locally.

David Daney


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