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SubjectNatSemi Geode improvement
Date
Hello,

NatSemi Geode has a several feature to speed up,
but reset defalut value is set to slow side.

I make a patch to speed up Geode about 20-40%!!
the benchmark result is downloadable from http://www.da-cha.org/geode/geode_graph.sxc.
that is openoffice format.

I use this patch with 2.4.18, 2.4.19 in 4 month, I think it is stable enough.


diff -urB -x .config -x '*.[oasS]' -x '*.in' -x '*.rej' -x '*.orig' linux-2.5.43-orig/arch/i386/kernel/apm.c linux-2.5.43/arch/i386/kernel/apm.c
diff -urB -x .config -x '*.[oasS]' -x '*.in' -x '*.rej' -x '*.orig' linux-2.5.43-orig/arch/i386/kernel/cpu/cyrix.c linux-2.5.43/arch/i386/kernel/cpu/cyrix.c
--- linux-2.5.43-orig/arch/i386/kernel/cpu/cyrix.c 2002-10-12 13:21:34.000000000 +0900
+++ linux-2.5.43/arch/i386/kernel/cpu/cyrix.c 2002-10-14 21:34:57.000000000 +0900
@@ -1,3 +1,7 @@
+/*
+ * NSC Geode improvments
+ * Hiroshi Miura <miura@da-cha.org>, June, 2002.
+ */
#include <linux/init.h>
#include <linux/bitops.h>
#include <linux/delay.h>
@@ -105,6 +109,65 @@
}
}

+static void __init set_cx86_reorder(void)
+{
+ unsigned char ccr3;
+ unsigned long flags;
+
+ printk(KERN_INFO "Enable Memory access reorder on Cyrix/NSC processor.\n");
+ local_irq_save(flags);
+ ccr3 = getCx86(CX86_CCR3);
+ setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
+ /* Load/Store Serialize to mem access disable (=reorder it) */
+ setCx86(CX86_PCR0, getCx86(CX86_PCR0) & ~0x80);
+#ifdef CONFIG_NOHIGHMEM
+ /* set load/store serialize from 1GB to 4GB */
+ ccr3 |= 0xe0;
+#endif
+ setCx86(CX86_CCR3, ccr3);
+ local_irq_restore(flags);
+}
+
+static void __init set_cx86_memwb(void)
+{
+ unsigned long cr0;
+ unsigned long flags;
+
+ printk(KERN_INFO "Enable Memory-Write-back mode on Cyrix/NSC processor.\n");
+ local_irq_save(flags);
+ /* CCR2 bit 2: unlock NW bit */
+ setCx86(CX86_CCR2, getCx86(CX86_CCR2) & ~0x04);
+ /* set 'Not Write-through' */
+ cr0 = 0x20000000;
+ __asm__("movl %%cr0,%%eax\n\t"
+ "orl %0,%%eax\n\t"
+ "movl %%eax,%%cr0\n"
+ : : "r" (cr0)
+ :"ax");
+ /* CCR2 bit 2: lock NW bit and set WT1 */
+ setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x14 );
+ local_irq_restore(flags);
+}
+
+static void set_cx86_inc(void)
+{
+ unsigned char ccr3;
+ unsigned long flags;
+
+ printk(KERN_INFO "Enable Incrementor on Cyrix/NSC processor.\n");
+ local_irq_save(flags);
+ ccr3 = getCx86(CX86_CCR3);
+ setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
+ /* PCR1 -- Performance Control */
+ /* Incrementor on, whatever that is */
+ setCx86(CX86_PCR1, getCx86(CX86_PCR1) | 0x02);
+ /* PCR0 -- Performance Control */
+ /* Incrementor Margin 10 */
+ setCx86(CX86_PCR0, getCx86(CX86_PCR0) | 0x04);
+ setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
+ local_irq_restore(flags);
+}
+
static void __init init_cyrix(struct cpuinfo_x86 *c)
{
unsigned char dir0, dir0_msn, dir0_lsn, dir1 = 0;
@@ -170,7 +233,7 @@
c->coma_bug = 1;
break;

- case 4: /* MediaGX/GXm */
+ case 4: /* MediaGX/GXm or Geode GXM/GXLV/GX1 */
#ifdef CONFIG_PCI
/* It isn't really a PCI quirk directly, but the cure is the
same. The MediaGX has deep magic SMM stuff that handles the
@@ -191,26 +250,37 @@

/* GXm supports extended cpuid levels 'ala' AMD */
if (c->cpuid_level == 2) {
- /* Enable Natsemi MMX extensions */
- setCx86(CX86_CCR7, getCx86(CX86_CCR7) | 1);
+ if (((0x54 >= dir1) && (dir1 >= 0x50))
+ || (dir1 >= 0x63)) { /* NSC Geode GXlv/GXm/GX1 */
+ /* I dont know about Cyrix GXm/GXi */
+ unsigned char ccr3, ccr4;
+ unsigned long flags;
+
+ local_irq_save(flags);
+ ccr3 = getCx86(CX86_CCR3);
+ setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
+ ccr4 = getCx86(CX86_CCR4);
+ ccr4 |= (0x20 /* fpu fast */
+ | 0x10 /* dte cache */
+ | 0x08); /* mem bypass */
+ setCx86(CX86_CCR4, ccr4);
+ setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
+ local_irq_restore(flags);
+
+ set_cx86_memwb(); /* L2 cache write-back mode */
+ set_cx86_reorder(); /* re-order mem write/read */
+ set_cx86_inc(); /* incrementor enable */
+ }
+ /* Enable cxMMX extensions (GX1 Datasheet 54) */
+ setCx86(CX86_CCR7, getCx86(CX86_CCR7)|1);

get_model_name(c); /* get CPU marketing name */
/*
* The 5510/5520 companion chips have a funky PIT
* that breaks the TSC synchronizing, so turn it off
*/
if (pci_find_device(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5510, NULL) ||
pci_find_device(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5520, NULL))
clear_bit(X86_FEATURE_TSC, c->x86_capability);
return;
}
else { /* MediaGX */
Cx86_cb[2] = (dir0_lsn & 1) ? '3' : '4';
p = Cx86_cb+2;
c->x86_model = (dir1 & 0x20) ? 1 : 2;
#ifndef CONFIG_CS5520
clear_bit(X86_FEATURE_TSC, c->x86_capability);
#endif
}
break;

diff -urB -x .config -x '*.[oasS]' -x '*.in' -x '*.rej' -x '*.orig' linux-2.5.43-orig/include/asm-i386/processor.h linux-2.5.43/include/asm-i386/processor.h
--- linux-2.5.43-orig/include/asm-i386/processor.h 2002-10-12 13:21:05.000000000 +0900
+++ linux-2.5.43/include/asm-i386/processor.h 2002-10-14 17:15:38.000000000 +0900
@@ -91,7 +91,7 @@

extern void identify_cpu(struct cpuinfo_x86 *);
extern void print_cpu_info(struct cpuinfo_x86 *);
-extern void dodgy_tsc(void);
+extern int pit_latch_buggy;

/*
* EFLAGS bits
@@ -229,8 +229,11 @@
#define CX86_CCR5 0xe9
#define CX86_CCR6 0xea
#define CX86_CCR7 0xeb
+#define CX86_PCR0 0x20
+#define CX86_PCR1 0xf0
#define CX86_DIR0 0xfe
#define CX86_DIR1 0xff
+#define CX86_GCR 0xb8
#define CX86_ARR_BASE 0xc4
#define CX86_RCR_BASE 0xdc

-
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