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SubjectRe: NatSemi Geode improvement
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> +     printk(KERN_INFO "Enable Memory access reorder on Cyrix/NSC processor.\n");
> + local_irq_save(flags);
> + ccr3 = getCx86(CX86_CCR3);
> + setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
> + /* Load/Store Serialize to mem access disable (=reorder it) */
> + setCx86(CX86_PCR0, getCx86(CX86_PCR0) & ~0x80);
> +#ifdef CONFIG_NOHIGHMEM
> + /* set load/store serialize from 1GB to 4GB */
> + ccr3 |= 0xe0;
> +#endif
> + setCx86(CX86_CCR3, ccr3);

I dont think this is safe. You now need store fences on bus mastering
DMA. You should be able to reuse the IDT winchip code for that - I set
the winchip up for weak store ordering too, and its a big win (I also
saw about 30% on block copies)

Alan

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