Messages in this thread |  | | From | "Kimon Berlin" <> | Date | Mon, 27 Jan 1997 15:58:37 +0100 | Subject | Re: PPro write combining |
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> I downloaded the source to 2.1.22 and found no reference to enabling write > combining in the sources. I have the documentation on how to do it, a Pentium > Pro machine with a PCI video card and the Intel IDE accelerator. > > Are there any moves to add write combining to hardware initialisation? It is > fairly involved (you need to find the correct physical addresses to enable, > and then use IPI to synchronise it over all available processors). I might > need some help with the x86 assembly language stuff (I don't use instructions > like WMSR all that often :-), and the help of the linux-smp people will also > be necessary. > > The necessary MTRR setup should be (taken from Pentium Pro BIOS writer's > guide, p3-2): > > 0-640kb writeback (use a fixed MTRR) > B0000-BFFFF write combining (banked video memory; use a fixed MTRR) > C0000-DFFFF write back (use a fixed MTRR) ^^^^^^^^^^^ Bad idea if you have ROMs (use write-protect instead), or an ISA card that uses buffers or memory-mapped IO (use uncached instead). All the memory from 0 to (top of RAM) should be set by the BIOS.
> E0000-FFFFF write protect (use a fixed MTRR) > 100000-top write back (use a variable MTRR pair) > linear fb write combining (use a variable MTRR pair)
Some BIOSes will set the linear frame buffer, but not all. The kernel may have to do it all by itself.
Generally speaking, MTRRs 0 through 5 are used by the BIOS, MTRRs 6 and 7 are available to the OS.
> That would leave two variable MTRR's for us to use for other things, like > setting up write combining for any other device that supports it. This > configuration gives the highest possible performance on Pentium Pro machines. > > I had started upon a root-level source in C++, but found that doing this > stuff live would probably freak out the OS, and the best way to do it is at > hardware initialization time. > > We can also look at the write posting bit on machines with an Orion > chipset. If it's off it would be nice to warn the user; something along the > lines of: > > HW init: broken Orion PCIset, write posting disabled. See your hardware > vendor for a replacement logic board. > > I'm in negotiations with HP about my HP Vectra VT 6/150 which has a broken > Orion 450KX PCIset. I didn't pay an outlandish sum for a broken computer, and > others shouldn't either. It took me a long time to identify the problem, > research it, and benchmark it to HP's satisfaction. I think it is particularly > galling that vendors can sell something that manages a paltry 5.8 MB/s cpu-pci > throughput, particularly on high end equipment.
Interesting. What equipment are you using? If it is IO-mapped, you will get low results no matter what, since both the CPU and chipset have high latency.
Cheers, Kimon (not exactly an unbiased third party regarding the Vectra VT6)
-- Kimon Berlin - Hewlett-Packard Performance Desktop Computing Operation R&D (BIOS), a spinoff of the Division Formerly Known as GPCD "You can tune a filesystem, but you can't tune a fish" [HP/UX tunefs(1M)]
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