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Subject[PATCH v2] arm64: dts: mediatek: Add cpufreq nodes for MT8192
Date
Add the cpufreq nodes for MT8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
Change in v1:
Fix : this should be <&performance 0>
[Allen-KH Cheng <allen-kh.cheng@mediatek.com>]
---
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 87b91c8feaf9..48a4fc88fde4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -70,6 +70,7 @@
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
capacity-dmips-mhz = <530>;
};

@@ -87,6 +88,7 @@
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
capacity-dmips-mhz = <530>;
};

@@ -104,6 +106,7 @@
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
capacity-dmips-mhz = <530>;
};

@@ -121,6 +124,7 @@
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
capacity-dmips-mhz = <530>;
};

@@ -138,6 +142,7 @@
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
+ performance-domains = <&performance 0>;
capacity-dmips-mhz = <1024>;
};

@@ -155,6 +160,7 @@
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
+ performance-domains = <&performance 0>;
capacity-dmips-mhz = <1024>;
};

@@ -172,6 +178,7 @@
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
+ performance-domains = <&performance 0>;
capacity-dmips-mhz = <1024>;
};

@@ -189,6 +196,7 @@
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
+ performance-domains = <&performance 0>;
capacity-dmips-mhz = <1024>;
};

@@ -318,6 +326,12 @@
compatible = "simple-bus";
ranges;

+ performance: performance-controller@11bc10 {
+ compatible = "mediatek,cpufreq-hw";
+ reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
+ #performance-domain-cells = <1>;
+ };
+
gic: interrupt-controller@c000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <4>;
--
2.18.0
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