Messages in this thread | | | Date | Fri, 3 Mar 2023 12:23:56 +0100 | Subject | Re: [PATCH v2] arm64: dts: mediatek: Add cpufreq nodes for MT8192 | From | AngeloGioacchino Del Regno <> |
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Il 03/03/23 03:00, Allen-KH Cheng ha scritto: > Add the cpufreq nodes for MT8192 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > --- > Change in v1: > Fix : this should be <&performance 0>
I didn't say that *all of them should be <&performance 0>.
It's 0 for the cortex-a55 CPUs and it's 1 for the A76 CPUs.
Please fix it.
> [Allen-KH Cheng <allen-kh.cheng@mediatek.com>] > --- > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index 87b91c8feaf9..48a4fc88fde4 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -70,6 +70,7 @@ > d-cache-line-size = <64>; > d-cache-sets = <128>; > next-level-cache = <&l2_0>; > + performance-domains = <&performance 0>; > capacity-dmips-mhz = <530>; > }; > > @@ -87,6 +88,7 @@ > d-cache-line-size = <64>; > d-cache-sets = <128>; > next-level-cache = <&l2_0>; > + performance-domains = <&performance 0>; > capacity-dmips-mhz = <530>; > }; > > @@ -104,6 +106,7 @@ > d-cache-line-size = <64>; > d-cache-sets = <128>; > next-level-cache = <&l2_0>; > + performance-domains = <&performance 0>; > capacity-dmips-mhz = <530>; > }; > > @@ -121,6 +124,7 @@ > d-cache-line-size = <64>; > d-cache-sets = <128>; > next-level-cache = <&l2_0>; > + performance-domains = <&performance 0>; > capacity-dmips-mhz = <530>; > };
It's 0 until there.
> > @@ -138,6 +142,7 @@ > d-cache-line-size = <64>; > d-cache-sets = <256>; > next-level-cache = <&l2_1>; > + performance-domains = <&performance 0>;
Here, and later (for cortex-a76), it's <&performance 1>.
Regards, Angelo
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