Messages in this thread | | | From | Martin Blumenstingl <> | Subject | [PATCH 0/3] - clk: meson8b: add the (read-only) video clock trees | Date | Sun, 2 Dec 2018 22:42:17 +0100 |
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This is the Meson8b variant of Neil's series from [0] called "- clk: meson: Add video clocks path". GXBB and newer use a -- vid_pll divider IP block which doesn't exist on the 32-bit SoCs. Instead the 32-bit SoCs use three simple dividers, a few muxes and some fixed dividers.
I used Neil's GXBB patches as initial reference, together with Amlogic's 3.10 kernel sources (drivers/amlogic/display/vout/enc_clk_config.c): [1]
With Jianxin's help I was able to get the clock tree into a state where the code is now able to recalculate the frequencies of the video clocks. I am using the clock measurer as "expected" values, together with the data from enc_clk_config.c where all the dividers are documented. My test protocol on Meson8b and Meson8m2 is attached below.
One note for all brave people who look at enc_clk_config.c from Amlogic's 3.10 kernel: some frequencies seem to be doubled there. VMODE_1080P is defined with hpll_clk_out = 2970, but it's only using the following PLL parameters: M = 61, N = 1, FRAC = 3584. At first I though that there's a pre-multiplier like on GXBB, but after digging deeper into the code I don't believe that pre-multiplier exists. The reason for this is for example VMODE_1080P_30HZ which uses hpll_clk_out = 1485 with the same PLL parameters as 2970 MHz. However, since the current code can recalculate the frequencies correctly I will leave it to a future patch to solve this "frequency doubling" - more work is needed anyways for actually changing the PLL's frequency (as there are many bits in HHI_VID_PLL_CNTL2, HHI_VID_PLL_CNTL3, HHI_VID_PLL_CNTL4 and HHI_VID_PLL_CNTL5 which the Amlogic 3.10 kernel is changing together with the M/N/FRAC values.
[0] https://patchwork.kernel.org/cover/10670657/ [1] https://github.com/endlessm/linux-meson/blob/cd4096c3ff4eb5b8a8a5581bb46508601c5470dc/drivers/amlogic/display/vout/enc_clk_config.c
1080P / Meson8b Odroid-C1 - u-boot: -- odroidc#video dev open 1080P -- mode = 8 vic = 16 -- set HDMI vic: 16 -- mode is: 8 -- viu chan = 1 -- config HPLL -- config HPLL done -- reconfig packet setting done - clkmsr: -- vid_pll 148497596 +/-4807Hz -- encp 148497596 +/-4807Hz -- encl 0 +/-3125Hz -- hdmi_ch0_tmds 148500000 +/-4807Hz -- hdmi_tx_pixel 148497596 +/-4807Hz - clk: -- hdmi_pll_dco 0 0 0 1485000000 0 0 50000 -- vid_pll 0 0 0 148500000 0 0 50000 -- cts_encp 0 0 0 148500000 0 0 50000 -- cts_encl 0 0 0 148500000 0 0 50000 -- hdmi_tx_pixel 0 0 0 148500000 0 0 50000
720P / Meson8b Odroid-C1 - u-boot: -- odroidc#video dev open 720P -- mode = 6 vic = 4 -- set HDMI vic: 4 -- mode is: 6 -- viu chan = 1 -- config HPLL -- config HPLL done -- reconfig packet setting done - clkmsr: -- vid_pll 148497596 +/-4807Hz -- encp 148497596 +/-4807Hz -- encl 0 +/-3125Hz -- hdmi_ch0_tmds 74250000 +/-3125Hz -- hdmi_tx_pixel 74248438 +/-3125Hz - clk: -- hdmi_pll_dco 0 0 0 1485000000 0 0 50000 -- vid_pll 0 0 0 148500000 0 0 50000 -- cts_encp 0 0 0 148500000 0 0 50000 -- cts_encl 0 0 0 148500000 0 0 50000 -- hdmi_tx_pixel 0 0 0 74250000 0 0 50000
480P / Meson8b Odroid-C1 - u-boot: -- odroidc#video dev open 480P -- mode = 2 vic = 3 -- set HDMI vic: 3 -- mode is: 2 -- viu chan = 1 -- config HPLL -- config HPLL done -- reconfig packet setting done - clkmsr: -- vid_pll 215996528 +/-6944Hz -- encp 53998438 +/-3125Hz -- encl 0 +/-3125Hz -- hdmi_ch0_tmds 26998438 +/-3125Hz -- hdmi_tx_pixel 27000000 +/-3125Hz - clk: -- hdmi_pll_dco 0 0 0 1080000000 0 0 50000 -- vid_pll 0 0 0 216000000 0 0 50000 -- cts_encp 0 0 0 54000000 0 0 50000 -- cts_encl 0 0 0 54000000 0 0 50000 -- hdmi_tx_pixel 0 0 0 27000000 0 0 50000
4K2K30HZ / Meson8m2 M8S - u-boot: -- m8m2_n200_v1#video dev open 4K2K30HZ -- mode = 13 vic = 68 -- set HDMI vic: 68 -- config HPLL -- config HPLL done -- reconfig packet setting done - clkmsr: -- vid_pll 297000000 +/-10416Hz -- encp 296989583 +/-10416Hz -- encl 296989583 +/-10416Hz -- hdmi_ch0_tmds 296984375 +/-10416Hz -- hdmi_tx_pixel 296979167 +/-10416Hz -- hdmi_sys 23998438 +/-3125Hz - clk: -- hdmi_pll_dco 0 0 0 1485000000 0 0 50000 -- vid_pll 0 0 0 297000000 0 0 50000 -- cts_encp 0 0 0 297000000 0 0 50000 -- cts_encl 0 0 0 297000000 0 0 50000 -- hdmi_tx_pixel 0 0 0 297000000 0 0 50000 -- hdmi_sys 0 0 0 24000000 0 0 50000
1080P / Meson8m2 M8S - u-boot: -- m8m2_n200_v1#video dev open 1080P -- mode = 8 vic = 16 -- set HDMI vic: 16 -- config HPLL -- config HPLL done -- reconfig packet setting done - clkmsr: -- vid_pll 148500000 +/-4807Hz -- encp 148500000 +/-4807Hz -- encl 148497596 +/-4807Hz -- hdmi_ch0_tmds 148497596 +/-4807Hz -- hdmi_tx_pixel 148497596 +/-4807Hz -- hdmi_sys 24000000 +/-3125Hz - clk: -- hdmi_pll_dco 0 0 0 1485000000 0 0 50000 -- vid_pll 0 0 0 148500000 0 0 50000 -- cts_encp 0 0 0 148500000 0 0 50000 -- cts_encl 0 0 0 148500000 0 0 50000 -- hdmi_tx_pixel 0 0 0 148500000 0 0 50000 -- hdmi_sys 0 0 0 24000000 0 0 50000
720P / Meson8m2 M8S - u-boot: -- m8m2_n200_v1#video dev open 720P -- mode = 6 vic = 4 -- set HDMI vic: 4 -- config HPLL -- config HPLL done -- reconfig packet setting done - clkmsr: -- vid_pll 148500000 +/-4807Hz -- encp 148500000 +/-4807Hz -- encl 148497596 +/-4807Hz -- hdmi_ch0_tmds 74248438 +/-3125Hz -- hdmi_tx_pixel 74248438 +/-3125Hz -- hdmi_sys 24000000 +/-3125Hz - clk: -- hdmi_pll_dco 0 0 0 1485000000 0 0 50000 -- vid_pll 0 0 0 148500000 0 0 50000 -- cts_encp 0 0 0 148500000 0 0 50000 -- cts_encl 0 0 0 148500000 0 0 50000 -- hdmi_tx_pixel 0 0 0 74250000 0 0 50000 -- hdmi_sys 0 0 0 24000000 0 0 50000
480P / Meson8m2 M8S - u-boot: -- m8m2_n200_v1#video dev open 480P -- mode = 2 vic = 3 -- set HDMI vic: 3 -- config HPLL -- config HPLL done -- reconfig packet setting done - - clkmsr: -- vid_pll 215996528 +/-6944Hz -- encp 54000000 +/-3125Hz -- encl 53998438 +/-3125Hz -- hdmi_ch0_tmds 27000000 +/-3125Hz -- hdmi_tx_pixel 27000000 +/-3125Hz -- hdmi_sys 24000000 +/-3125Hz - - clk: -- hdmi_pll_dco 0 0 0 1080000000 0 0 50000 -- vid_pll 0 0 0 216000000 0 0 50000 -- cts_encp 0 0 0 54000000 0 0 50000 -- cts_encl 0 0 0 54000000 0 0 50000 -- hdmi_tx_pixel 0 0 0 27000000 0 0 50000 -- hdmi_sys 0 0 0 24000000 0 0 50000
Martin Blumenstingl (3): - clk: meson: meson8b: fix the offset of -- vid_pll_dco's N value - clk: meson: meson8b: add the fractional divider for -- vid_pll_dco - clk: meson: meson8b: add the read-only video clock trees
drivers/clk/meson/meson8b.c | 746 +++++++++++++++++++++++++++++++++++- drivers/clk/meson/meson8b.h | 54 ++- 2 files changed, 789 insertions(+), 11 deletions(-)
-- 2.19.2
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