Messages in this thread | | | From | Aravind Gopalakrishnan <> | Subject | [PATCH 0/4] Enable deferred error interrupts | Date | Thu, 30 Apr 2015 09:49:21 -0500 |
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Newer AMD processors can generate deferred errors and can be configured to generate APIC interrupts on such events.
This patchset introduces a new interrupt handler for deferred errors and configures the HW if the feature is present.
Patch1: Defines SUCCOR cpuid bit. This indicates prescence of features such as data poisoning and deferred error interrupts in hardware. Patch2: Implement the interrupt handler. - setup vector number, build the interrupt and implement handler function in this patch. Patch3, Patch 4: Cleanups in the code. No functional changes are introduced.
Aravind Gopalakrishnan (4): x86/mce: Define 'SUCCOR' cpuid bit x86/mce/amd: Introduce deferred error interrupt handler x86, irq: Cleanup ordering of vector numbers x86/mce/amd: Rename setup_APIC_mce
arch/x86/include/asm/entry_arch.h | 3 + arch/x86/include/asm/hardirq.h | 3 + arch/x86/include/asm/hw_irq.h | 2 + arch/x86/include/asm/irq_vectors.h | 11 ++-- arch/x86/include/asm/mce.h | 6 +- arch/x86/include/asm/trace/irq_vectors.h | 6 ++ arch/x86/include/asm/traps.h | 3 +- arch/x86/kernel/cpu/mcheck/mce.c | 1 + arch/x86/kernel/cpu/mcheck/mce_amd.c | 105 ++++++++++++++++++++++++++++++- arch/x86/kernel/entry_64.S | 5 ++ arch/x86/kernel/irq.c | 6 ++ arch/x86/kernel/irqinit.c | 4 ++ arch/x86/kernel/traps.c | 4 ++ 13 files changed, 150 insertions(+), 9 deletions(-)
-- 1.9.1
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