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    SubjectRe: Ordering between PCI config space writes and MMIO reads?
    Quoting r. Matthew Wilcox <matthew@wil.cx>:
    > Subject: Re: Ordering between PCI config space writes and MMIO reads?
    >
    > On Tue, Oct 24, 2006 at 02:51:30PM -0700, Roland Dreier wrote:
    > > > I think the right way to fix this is to ensure mmio write ordering in
    > > > the pci_write_config_*() implementations. Like this.
    > >
    > > I'm happy to fix this in the PCI core and not force drivers to worry
    > > about this.
    > >
    > > John, can you confirm that this patch fixes the issue for you?
    >
    > Hang on. I wasn't thinking clearly. mmiowb() only ensures the write
    > has got as far as the shub. There's no way to fix this in the pci core
    > -- any PCI-PCI bridge can reorder the two.
    >
    > This is only really a problem for setup (when we program the BARs), so
    > it seems silly to enforce an ordering at any other time. Reluctantly, I
    > must disagree with Jeff -- drivers need to fix this.

    This can be true for any bridge.
    Most arches, however, simply block until config write completes - this is why
    driver doesn't issue any MMIO writes - and this is what we are looking for here
    - a way to block the CPU until split completion for config write arrives.

    By the way, e.g. the PCI Express spec says:
    "Read Requests and I/O or Configuration Write Requests are permitted to be
    blocked by or to pass other Read Requests and I/O or Configuration Write Requests."
    so it is not clear that doing a config read will always flush all config writes
    as you want.

    --
    MST
    -
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