Messages in this thread | | | Subject | Dual core Athlons and unsynced TSCs | From | Lee Revell <> | Date | Thu, 12 Jan 2006 17:17:39 -0500 |
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It's been known for quite some time that the TSCs are not synced between cores on Athlon X2 machines and this screws up the kernel's timekeeping, as it still uses the TSC as the default time source on these machines.
This problem still seems to be present in the latest kernels. What is the plan to fix it? Is the fix simply to make the kernel use the ACPI PM timer by default on Athlon X2?
Lee
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