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SubjectRe: L2 cache detection in Celeron 2GHz (P4 based)
On Wed, Mar 19, 2003 at 09:18:04AM +0100, Paul Rolland wrote:

> You can also add that the L1 detection doesn't seem to be correct
> either :
> 0K Instruction cache, and 8K data cache for L1... This is not much
> for instruction, it seems it should be 12K...

That should be fixed in recent 2.4s (and not-so-recent 2.5s).
What version are you seeing this problem on?

Dave

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