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SubjectRe: L2 cache detection in Celeron 2GHz (P4 based)
On Wed, Mar 19, 2003 at 08:47:43AM +0200, Juha Poutiainen wrote:

> x86info shows that there is something with descriptor 0x3b, and 0x3c
> seems to be 256K L2 cache. So I guess it is as simple as adding a line:
> { 0x3B, LVL_2, 128 },
> in arch/i386/kernel/setup.c after line 2204 (2.4.20) and
> in arch/i386/kernel/cpu/intel.c after line 102 (2.5.65)

Yep, that's exactly the right fix.
x86info cvs updated, and 2.5 patch queued for Linus.
I'll do a 2.4 patch later if you haven't already done so.

> I've tried both, they seems to report it fine, but I can't be sure if
> that really is correct id of that cache. Celeron at issue has 128K L2
> cache.

Intel document 24161822.pdf confirms it.


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