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SubjectRe: New resources - pls, explain :-(
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>>>>> "Peter" == Peter Desnoyers <pjd@fred001.dynip.com> writes:

Peter> Consider the following sequence of driver events:

Peter> 1. adapter DMAs into host memory 2. DMA completes 3. host reads
Peter> DMA-ed data out of host memory

Peter> A non-cache-coherent bus means that you need to insert a magic
Peter> step between 2 and 3 to guarantee that the CPU reads the new
Peter> data. (it also affects the opposite process, where the CPU
Peter> writes to host memory, and then the adapter DMAs out of it)

The correct place to put this is in front of 1, ie. before you even
start the DMA.

Jes

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