Messages in this thread | | | Subject | Re: New resources - pls, explain :-( | From | Jes Sorensen <> | Date | 17 Aug 1999 19:34:51 +0200 |
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>>>>> "Peter" == Peter Desnoyers <pjd@fred001.dynip.com> writes:
Peter> Jes Sorensen wrote: >> The correct place to put this is in front of 1, ie. before you >> even start the DMA.
Peter> As always, it depends. The UltraSparc can leave bits of the Peter> DMA'ed data in its PCI bridges after the transfer completes, Peter> and you need to explicitly flush the bus to make sure host Peter> memory and cache is in sync with the device. Unless you've Peter> mapped the region in slow, synchronous mode. Or so their Peter> documentation states - I've heard that real hardware behavior Peter> isn't actually as bad as they tell Solaris driver writers.
This is a different issue, what I was referring to is CPU vs. memory coherency - what you describe is PCI vs memory coherency. You'd normally like to simply invalidate the pages involved early so they can be used by the CPU for other areas while it is doing other things. How to handle the case you describe is kinda nasty since I asume it will cause some busy waiting (or an extra interrupt phase) if one has to go in and tell the bus to finish up befrore continuing.
Jes
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