lkml.org 
[lkml]   [1999]   [Aug]   [17]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
SubjectRe: New resources - pls, explain :-(
From
Date
>>>>> "Peter" == Peter Desnoyers <pjd@fred001.dynip.com> writes:

Peter> Jes Sorensen wrote:
>> The correct place to put this is in front of 1, ie. before you
>> even start the DMA.

Peter> As always, it depends. The UltraSparc can leave bits of the
Peter> DMA'ed data in its PCI bridges after the transfer completes,
Peter> and you need to explicitly flush the bus to make sure host
Peter> memory and cache is in sync with the device. Unless you've
Peter> mapped the region in slow, synchronous mode. Or so their
Peter> documentation states - I've heard that real hardware behavior
Peter> isn't actually as bad as they tell Solaris driver writers.

This is a different issue, what I was referring to is CPU vs. memory
coherency - what you describe is PCI vs memory coherency. You'd
normally like to simply invalidate the pages involved early so they
can be used by the CPU for other areas while it is doing other
things. How to handle the case you describe is kinda nasty since I
asume it will cause some busy waiting (or an extra interrupt phase) if
one has to go in and tell the bus to finish up befrore continuing.

Jes

-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.rutgers.edu
Please read the FAQ at http://www.tux.org/lkml/

\
 
 \ /
  Last update: 2005-03-22 13:53    [W:1.709 / U:0.008 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site