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SubjectRe: New resources - pls, explain :-(
Hi,
> The ideal situation is what the PCI spec says about transaction ordering.
> Basically (from memory):
> - - Strong ordering in each direction.
> - - The design of the whole PCI system must ensure that no deadlock or
> livelock may occur.
What about this: CPU cannot finish write cycle to G200 because of G200
command queue is full. G200 cannot empty slot in command queue because of
currently processed command requires access to PCI bus (to main memory) to
finish. Does this count as deadlock or livelock (*)? Is it possible to
handle this situation (limited resources on both videocard, host CPU
and bridge) correctly?
> But the reality is quite different:
> Some system-PCI bridges may:
> - - Reorder write to memory.
> - - Only flush on a read posted write transactions that go in the
> direction of this read transaction (donnot flush PWs in the opposite
> direction)
> - - Only ensure that everything is flushed prior to the interrupt delivery.
> - - Not snoop DMA accesses.
> - - Etc...
> There is no nightmare here, but just too much fun. ;-)
It cost couple of hours to find, why in busmastering mode my driver
painted (after matroxfb switches to graphics and redraws old vgacon screen)
just 832 1/2 character with 6x11 font, 20 1/3 with 12x22 font and INF with
8x16 font before complete lock (no poweroff button on ATX) occurs (**).
Petr Vandrovec
vandrove@vc.cvut.cz

(*) There are two variants - if you set 'noretry' option on matrox,
whole bus simple freezes forever. If you do not set 'noretry',
440BX retries write cycle without ever giving access to bus to other
busmasters, so no bonus again :-( Unplugging G200 from slot fixes
problem, so you can at least cleanly reboot.
(**) So I removed that code...

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