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SubjectRe: New resources - pls, explain :-(
"Petr Vandrovec Ing. VTEI" wrote:
> > The ideal situation is what the PCI spec says about transaction ordering.
> > Basically (from memory):
> > - - Strong ordering in each direction.
> > - - The design of the whole PCI system must ensure that no deadlock or
> > livelock may occur.

> What about this: CPU cannot finish write cycle to G200 because of G200
> command queue is full. G200 cannot empty slot in command queue because of
> currently processed command requires access to PCI bus (to main memory) to
> finish. Does this count as deadlock or livelock (*)? Is it possible to
> handle this situation (limited resources on both videocard, host CPU
> and bridge) correctly?

http://www.mooremusic.com.au/tech/vgakill.htm

This is a good link and talks about video devices locking up the bus
other such stuff. In general, you probably want an option in your
driver that tells it to check the FIFO instead of simply blocking until
you can write another accel command.

Jeff

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