Messages in this thread | | | Date | Thu, 12 Feb 1998 05:56:48 +0100 | From | ralf@uni-kobl ... | Subject | TLB entries > 4kb |
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Some architectures can use multiple page sizes in the TLB at the same time. This would for example allow to map memory allocations > PAGE_SIZE using just a single TLB entry if the circumstances are just right, thereby reducing / eleminating TLB trashing. This should improve the performance for huge apps quite a bit. Some architectures could partially get rid of the sick effects of their virtual indexed primary caches as well. All that is needed for this to work is to have sufficiently large physical pages with sufficient alignment at hand.
Has anybody ever looked into implementing that? What architectures besides MIPS could take advantage of such a feature?
Ralf
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