Messages in this thread | | | Date | Fri, 28 Feb 1997 13:45:41 +0100 (MET) | From | Stephan Meyer <> | Subject | Re: MSR support for x86 |
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On Fri, 28 Feb 1997, Ingo Molnar wrote: > btw, have you seen www.intel.com and www.x86.org already? LOTS of docs > there. I think the MSRs are described to some level in the P6 manuals.
good suggestion :)
> nice interface ;) I think the 'official' minor number can wait until this > gets into the kernel? You have choosen the correct major number :)
it's 10 142 now.
> have you tried putting NULL to the 'open' function?
yes, I have and it gave me a GPF. have a look at the code in ./drivers/char/misc.c the open function is called without checking for NULL
> one more thing. What do you think, where is the right place to put 'enable > cache/disable cache' functionality? They are driven through the cr[0123] > registers in the CPU, not through MSR. I think these two concepts should > be integrated somehow. Maybe writing to offset 0123 should set cr[0123] > (i would hard-coded mask off certain bits, nobody should be able to > disable paging accidentally :)
This is an interesting suggestion :) If we implement this, it should be tightly secured since any user could mess around with the 2nd level cache. A possible application could be a CPU manager!
I'd like comments on how to do it. It should be quite flexible to allow the addition of new instructions.
Mapping the control registers to MSR offsets is a bad idea since there might turn up some MSRs right there.
> but i dont know the details, only the final goal: to be able to 'mess > around' with machine specific settings in an integrated fashion.
In other words, to have fun. :)
> Ingo
Cheers, Stephan
----------------------------------------------- Stephan Meyer +49-89-4301114 Stephan.Meyer@munich.netsurf.de http://fatman.mathematik.tu-muenchen.de/~meyer/ -----------------------------------------------
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