Messages in this thread | | | Subject | Re: [PATCH RFC 1/2] clk: hisilicon: rename hi3519 PLL registration function | From | Stephen Boyd <> | Date | Wed, 10 Apr 2024 23:52:24 -0700 |
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Quoting Yang Xiwen via B4 Relay (2024-02-24 08:56:09) > diff --git a/drivers/clk/hisilicon/clk-hi3559a.c b/drivers/clk/hisilicon/clk-hi3559a.c > index ff4ca0edce06..77fa4203a428 100644 > --- a/drivers/clk/hisilicon/clk-hi3559a.c > +++ b/drivers/clk/hisilicon/clk-hi3559a.c > @@ -452,7 +452,7 @@ static const struct clk_ops hisi_clk_pll_ops = { > .recalc_rate = clk_pll_recalc_rate, > }; > > -static void hisi_clk_register_pll(struct hi3559av100_pll_clock *clks, > +static void _hisi_clk_register_pll(struct hi3559av100_pll_clock *clks,
Prefix it with hi3559a then to be SoC specific please. But this is also static so I'm not sure why this patch is needed at all.
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