Messages in this thread Patch in this message | | | From | Yang Xiwen via B4 Relay <> | Date | Sun, 25 Feb 2024 00:56:09 +0800 | Subject | [PATCH RFC 1/2] clk: hisilicon: rename hi3519 PLL registration function |
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From: Yang Xiwen <forbidden405@outlook.com>
Hi3559 clock drivers implemented their own PLL driver. Unfortunately our generic PLL driver will use a same name. So add a prefix "_" to avoid that.
Signed-off-by: Yang Xiwen <forbidden405@outlook.com> --- drivers/clk/hisilicon/clk-hi3559a.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/hisilicon/clk-hi3559a.c b/drivers/clk/hisilicon/clk-hi3559a.c index ff4ca0edce06..77fa4203a428 100644 --- a/drivers/clk/hisilicon/clk-hi3559a.c +++ b/drivers/clk/hisilicon/clk-hi3559a.c @@ -452,7 +452,7 @@ static const struct clk_ops hisi_clk_pll_ops = { .recalc_rate = clk_pll_recalc_rate, }; -static void hisi_clk_register_pll(struct hi3559av100_pll_clock *clks, +static void _hisi_clk_register_pll(struct hi3559av100_pll_clock *clks, int nums, struct hisi_clock_data *data, struct device *dev) { void __iomem *base = data->base; @@ -517,7 +517,7 @@ static struct hisi_clock_data *hi3559av100_clk_register( if (ret) return ERR_PTR(ret); - hisi_clk_register_pll(hi3559av100_pll_clks, + _hisi_clk_register_pll(hi3559av100_pll_clks, ARRAY_SIZE(hi3559av100_pll_clks), clk_data, &pdev->dev); ret = hisi_clk_register_mux(hi3559av100_mux_clks_crg, -- 2.43.0
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