Messages in this thread Patch in this message | | | Date | Mon, 24 Jul 2023 15:29:35 +0800 | From | sunran001@208suo ... | Subject | [PATCH] drm/amd/pm: Clean up errors in sienna_cichlid_ppt.c |
| |
Fix the following errors reported by checkpatch:
ERROR: space required after that ',' (ctx:VxV) ERROR: space required before the open parenthesis '(' ERROR: spaces required around that '=' (ctx:VxW)
Signed-off-by: Ran Sun <sunran001@208suo.com> --- .../drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index 0cda3b276f61..5c233eda09ee 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -78,7 +78,7 @@ (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\ else\ (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\ -} while(0) +} while (0)
/* STB FIFO depth is in 64bit units */ #define SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES 8 @@ -590,7 +590,7 @@ static int sienna_cichlid_tables_init(struct smu_context *smu)
static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu) { - struct smu_table_context *smu_table= &smu->smu_table; + struct smu_table_context *smu_tabl = &smu->smu_table; SmuMetricsExternal_t *metrics_ext = (SmuMetricsExternal_t *)(smu_table->metrics_table); uint32_t throttler_status = 0; @@ -711,7 +711,7 @@ static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu, MetricsMember_t member, uint32_t *value) { - struct smu_table_context *smu_table= &smu->smu_table; + struct smu_table_context *smu_table = &smu->smu_table; SmuMetrics_t *metrics = &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics); SmuMetrics_V2_t *metrics_v2 = @@ -1461,7 +1461,7 @@ static int sienna_cichlid_force_clk_levels(struct smu_context *smu, goto forec_level_out; break; case SMU_DCEFCLK: - dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n"); + dev_info(smu->adev->dev, "Setting DCEFCLK min/max dpm level is not supported!\n"); break; default: break; @@ -1881,7 +1881,7 @@ static int sienna_cichlid_read_sensor(struct smu_context *smu, uint16_t *temp; struct amdgpu_device *adev = smu->adev;
- if(!data || !size) + if (!data || !size) return -EINVAL;
switch (sensor) { @@ -2067,15 +2067,15 @@ static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal; uint32_t max_memory_clock = max_sustainable_clocks->uclock;
- if(smu->disable_uclk_switch == disable_memory_clock_switch) + if (smu->disable_uclk_switch == disable_memory_clock_switch) return 0;
- if(disable_memory_clock_switch) + if (disable_memory_clock_switch) ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0); else ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
- if(!ret) + if (!ret) smu->disable_uclk_switch = disable_memory_clock_switch;
return ret;
| |