Messages in this thread | | | Date | Fri, 23 Jun 2023 14:32:27 +0100 | From | Jonathan Cameron <> | Subject | Re: [PATCH v7 14/27] cxl/port: Store the port's Component Register mappings in struct cxl_port |
| |
On Thu, 22 Jun 2023 15:55:10 -0500 Terry Bowman <terry.bowman@amd.com> wrote:
> From: Robert Richter <rrichter@amd.com> > > CXL capabilities are stored in the Component Registers. To use them, > the specific I/O ranges of the capabilities must be determined by > probing the registers. For this, the whole Component Register range > needs to be mapped temporarily to detect the offset and length of a > capability range. > > In order to use more than one capability of a component (e.g. RAS and > HDM) the Component Register are probed and its mappings created > multiple times. This also causes overlapping I/O ranges as the whole > Component Register range must be mapped again while a capability's I/O > range is already mapped. > > Different capabilities cannot be setup at the same time. E.g. the RAS > capability must be made available as soon as the PCI driver is bound, > the HDM decoder is setup later during port enumeration. Moreover, > during early setup it is still unknown if a certain capability is > needed. A central capability setup is therefore not possible, > capabilities must be individually enabled once needed during > initialization. > > To avoid a duplicate register probe and overlapping I/O mappings, only > probe the Component Registers one time and store the Component > Register mapping in struct port. The stored mappings can be used later > to iomap the capability register range when enabling the capability, > which will be implemented in a follow-on patch. > > Signed-off-by: Robert Richter <rrichter@amd.com> > Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
| |