Messages in this thread Patch in this message | | | From | David Yang <> | Subject | [PATCH] phy: hisilicon: Adopt phy-hisi-inno-usb2 to ARM | Date | Thu, 16 Feb 2023 09:37:13 +0800 |
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Hisilicon also uses phy-hisi-inno-usb2 on some ARM32-only SoCs (for example, Hi3798), with a slightly different register convention.
Signed-off-by: David Yang <mmyangfl@gmail.com> --- drivers/phy/hisilicon/Kconfig | 2 +- drivers/phy/hisilicon/phy-hisi-inno-usb2.c | 16 ++++++++++++++-- 2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/hisilicon/Kconfig b/drivers/phy/hisilicon/Kconfig index d3b92c288..6c89136fc 100644 --- a/drivers/phy/hisilicon/Kconfig +++ b/drivers/phy/hisilicon/Kconfig @@ -54,7 +54,7 @@ config PHY_HISTB_COMBPHY config PHY_HISI_INNO_USB2 tristate "HiSilicon INNO USB2 PHY support" - depends on (ARCH_HISI && ARM64) || COMPILE_TEST + depends on ARCH_HISI || COMPILE_TEST select GENERIC_PHY select MFD_SYSCON help diff --git a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c index b133ae067..624899536 100644 --- a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c +++ b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c @@ -20,12 +20,24 @@ #define PHY_CLK_STABLE_TIME 2 /* unit:ms */ #define UTMI_RST_COMPLETE_TIME 2 /* unit:ms */ #define POR_RST_COMPLETE_TIME 300 /* unit:us */ + #define PHY_TEST_DATA GENMASK(7, 0) +#define PHY_TEST_ADDR_OFFSET 8 +#ifdef CONFIG_ARM64 #define PHY_TEST_ADDR GENMASK(15, 8) +#define PHY_TEST_PORT_OFFSET 16 #define PHY_TEST_PORT GENMASK(18, 16) #define PHY_TEST_WREN BIT(21) #define PHY_TEST_CLK BIT(22) /* rising edge active */ #define PHY_TEST_RST BIT(23) /* low active */ +#else +#define PHY_TEST_ADDR GENMASK(11, 8) +#define PHY_TEST_PORT_OFFSET 12 +#define PHY_TEST_PORT BIT(12) +#define PHY_TEST_WREN BIT(13) +#define PHY_TEST_CLK BIT(14) /* rising edge active */ +#define PHY_TEST_RST BIT(15) /* low active */ +#endif #define PHY_CLK_ENABLE BIT(2) struct hisi_inno_phy_port { @@ -47,8 +59,8 @@ static void hisi_inno_phy_write_reg(struct hisi_inno_phy_priv *priv, u32 val; val = (data & PHY_TEST_DATA) | - ((addr << 8) & PHY_TEST_ADDR) | - ((port << 16) & PHY_TEST_PORT) | + ((addr << PHY_TEST_ADDR_OFFSET) & PHY_TEST_ADDR) | + ((port << PHY_TEST_PORT_OFFSET) & PHY_TEST_PORT) | PHY_TEST_WREN | PHY_TEST_RST; writel(val, reg); -- 2.39.1
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