Messages in this thread | ![/](/images/icornerl.gif) | | From | Doug Anderson <> | Date | Mon, 20 Nov 2023 10:05:44 -0800 | Subject | Re: [PATCH V3] drm/panel: boe-tv101wum-nl6: Fine tune Himax83102-j02 panel HFP and HBP |
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Hi,
On Sun, Nov 19, 2023 at 6:01 PM Cong Yang <yangcong5@huaqin.corp-partner.google.com> wrote: > > The refresh reported by modetest is 60.46Hz, and the actual measurement > is 60.01Hz, which is outside the expected tolerance. Adjust hporch and > pixel clock to fix it. After repair, modetest and actual measurement were > all 60.01Hz. > > Modetest refresh = Pixel CLK/ htotal* vtotal, but measurement frame rate > is HS->LP cycle time(Vblanking). Measured frame rate is not only affecte > by Htotal/Vtotal/pixel clock, also affected by Lane-num/PixelBit/LineTime > /DSI CLK. Assume that the DSI controller could not make the mode that we > requested(presumably it's PLL couldn't generate the exact pixel clock?). > If you use a different DSI controller, you may need to readjust these > parameters. Now this panel looks like it's only used by me on the MTK > platform, so let's change this set of parameters. > > Fixes: 1bc2ef065f13 ("drm/panel: Support for Starry-himax83102-j02 TDDI MIPI-DSI panel") > Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com> > Reviewed-by: Douglas Anderson <dianders@chromium.org> > --- > Chage since V2: > > - Update commit message. > > V2: https://lore.kernel.org/all/20231117032500.2923624-1-yangcong5@huaqin.corp-partner.google.com > > Chage since V1: > > - Update commit message. > > V1: https://lore.kernel.org/all/20231110094553.2361842-1-yangcong5@huaqin.corp-partner.google.com > --- > drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-)
As per previous discussions, this seems OK to me. I'll give it one more day for anyone to speak up and then plan to land it.
-Doug
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